Integrated Memory controller for future Intel cpu?

[halkebul]

Does Intel plan to integrate the DDR SDRAM memory controller into future cpu's like AMD has done with K8 Athlon and opteron.

<i>It's your world kid!!!</i><P ID="edit"><FONT SIZE=-1><EM>Edited by halkebul on 10/10/02 12:45 PM.</EM></FONT></P>

 

[juin]

not in P4 maybe in Montecino or chivano.

Now what to do??

 

[halkebul]

"not in P4 maybe in Montecino or chivano"

Are there any noteworthy architectual technologies that we should be aware of for either Montecino or chivano?

<i>It's your world kid!!!</i>

 

[Kemche]

How in the world did you come up with this conclusion????

Does the fact that Intel has drifted away from Rambus (in prefrence to DDR SDRAM) mean that Intel plans to integrate the DDR SDRAM memory controller into future cpu's like AMD has done with K8 Athlon and opteron.

I don't think Intel's decision not to support RDRAM has anything to do with integrating Memory controller on their processor. I think it has a lot to do with the Company Rambus. I think intel and most of the poeple on the forum knows that RDRAM is the best memory for the P4's but the Rambus Company never wanted to lower their royalty fees. So the Mfgrs would have to pay Rambus a lot more money then they would have to pay for DDR. That's why the RDRAM Module's are more expensive. And that's why more people aren't adopting to RDRAM. And that's the reason Intel is drifting away from RDRAM.

KG

"Artificial intelligence is no match for natural stupidity." - Sarah Chambers

 

[halkebul]

"I think intel and most of the poeple on the forum knows that RDRAM is the best memory for the P4's but the Rambus Company never wanted to lower their royalty fees."

Much information here. Hmm. Will RDRAM be able to keep pace with DDR SDRAM over the long term? Explain.

<i>It's your world kid!!!</i>

 

[juin]

Bolt Montecino and chivano are update for the IA-64 ligne.

Madison 6mb L3 0.13 copper interconnecter maybe also 133mghz FSB
Montecino 12 mb L3 SMT 90 nm copper interconecter strained silicon.......
Chivano ????

Any of this CPU can be marvelize (reference to Alpha EV7 rdram built in memory controleur)

Now what to do??

 

[knewt]

Do you even know what you are talking about? I've never even heard of Chivano, but Montecito (not Montecino) is the code name for an upcomming enterprise platform. Has nothing to do with desktop mp.

 

[IIB]

Too bad most ppl would think of it as "Opteronize"
anyway remeber the <b>architectural design</b> of such cpus is done ~3-5 years before they tap.
Maybe the exDECers had more to do with physical design, circuit design and so forth...


This post is best viewed with common sense enabled<P ID="edit"><FONT SIZE=-1><EM>Edited by iib on 10/11/02 02:55 AM.</EM></FONT></P>

 

[Victory]

Most of the people here are a younger crowd, I doubt many of them know even who DEC was


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[Dark_Archonis]

Montecito is rumoured to have hyperthreading, and chivano is rumoured to go dual-core (sometime around 2005/2006). It is supposed to be on 65nm process. Also, Chivano might use SOI, not sure though.

knewt, just because you've never heard of chivano doesn't mean it doesn't exist. That would be looking at the world in a narrow point of view. Chivano does exist, it's the successor to Montecito, which is the successor to Madison. Intel is promising all CPU's in the "Itanium" line will be pin compatible, and who ever said anything about desktop mp? Itanium was never meant to for desktop mp, it was always meant for enterprise/high end server area.

To answer the original poster's question, Intel probably won't put an integrated MCH into it's future CPU's, becuase it doesn't need to (for now). Intel might put it into future Itaniums though for maximum performance.

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[eden]

Um dude, P4s desperatly feed on low latency. If there is anything RDRAM is holding back, it's latency. An MCH, modular, would save the day, it'd have most likely an even more significant performance boost than the Hammer's integration, because P4s require low latency to keep their high clock speeds well used.

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[imgod2u]

I wouldn't say so with the prefetch logic on the current P4's. What it needs is a bigger cache not to mention a high-bandwidth memory subsystem.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[juin]

At Aceshardware show that on 64KB block RDRAM have less latency that DDR 333 about 20% more on 128 block.A new chipset can reduce latency be 10% to 15%

Now what to do??

 

[juin]

Montecito is rumoured to have hyperthreading

Nothing say that HT as we know it in P7.There a chance that they put a mix of EV8 SMT and P7 HT.

Pi compatible for madison yes nothing say about montecino and higher.

Now what to do??

 

[slvr_phoenix]

Um dude, P4s desperatly feed on low latency. If there is anything RDRAM is holding back, it's latency. An MCH, modular, would save the day, it'd have most likely an even more significant performance boost than the Hammer's integration, because P4s require low latency to keep their high clock speeds well used.

Sorry Eden, but I've got to disagree with you. Yes, RDRAM has a high latency. But the P4 doesn't much suffer for it.

One thing that Intel has done well though is their prefetching. Because of this, the prefetch is able to negate an awful lot of the memory's latency. So the only thing that low-latency memory would actually improve are the times when the P4's predictions are wrong and thus the prefetch misses. And even then, with the large cache sizes of the Northwoods and beyond, this is getting more and more negated.

This is one area where AMD could <b>really</b> learn to improve their cores. Instead though, because AMD does mispredict a lot more than Intel and because AMD has less cache, the Athlons practically live or die by the memory latency.

P4's however suffer far less from slow memory. Which is why bandwidth is usually much more important for a P4 than latency is, hence RDRAM from the evil Rambus. (And hence no RDRAM for the Athlon, because an AMD + RDRAM system would be as mismatched as putting SDR SDRAM on a P4.)

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[eden]

My bad then, I always learn something new!

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[juin]

On top of that HT negate a lot of lantency but increase the need in bandwith.

Now what to do??

 

[juin]

On the athlon side in spec bench there were a great improvement moving to 166 FSB due to more bandwith

Now what to do??

 

[imgod2u]

At 2+ GHz maybe. Anand's, Toms and even X-Bitlab's benches for the 1.73 and 1.8 GHz Athlons showed less than 5% improvement when moving from 133 to 166.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[juin]

It relate only to spec benchmark

Now what to do??

 

[eden]

I would think it's because of the better Nforce 2 controller, not the 166MHZ only by itself.

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[imgod2u]

I didn't see that much of an improvement in nForce 2 either. Compared to the KT333 with 133MHz FSB, it didn't offer that big an improvement in the majority of benchmarks. A few selected few maybe. But then again, it did have double the memory bandwidth, just that not all of it was dedicated to the processor.

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[eden]

You'd be the only one who didn't see all the improvement.
For example between the XP2600 and the XP2700 which was a simple 33MHZ higher, there was a significant IPC boosts, often ranging from 10-15%, you can easily deduct that without even calculating simply by looking at the difference visually.
That's a pretty big boost, and yet it couldn't entirely win, but at least go back UP there.

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[juin]

chipset not influence the score in spec bench

Now what to do??

 

[eden]

In viewperf I saw a significant improvement, it lead in all tests, while previously it lost in almost all except one where it is nearly twice better. Also if it's not chipset then how come the 166MHZ FSB tests on KT333 previously did not show THIS much improvement, compared to Nforce 2?

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