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Happy Holidays everyone! IEDM information recap to think about over the Holidays!
IEDM 2017 - Intel Versus GLOBALFOUNDRIES at the Leading Edge
by Scotten Jones
Published on 12-17-2017 06:00 AM
IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV
David SchorIEDM 2017, Process TechnologiesDecember 21, 2017
GlobalFoundries will have the smaller cell, but Intel will still have about ~13.8-19.6% better logic density, (published estimates)Intel's ~102.9-103 MTr/mm² to GoFlo's ~86-90.5 MTr/mm², because Intel is using contact over active gate. Intel reports 100.8 MTr/mm² for their own process making it only about 11% logic density gap compared to Scotten Jones estimate of 90.5MTr/mm². That being said, GlobalFoundries have made significant improvements to their transistors! And they will be on as close to level playing field that we have seen, and will end up being a contest mainly between who has the best design.
IEDM 2017: Intel’s 10nm Platform Process
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By Dick James
Contact over active gate
IEDM 2017 - Intel Versus GLOBALFOUNDRIES at the Leading Edge
by Scotten Jones
Published on 12-17-2017 06:00 AM
IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV
David SchorIEDM 2017, Process TechnologiesDecember 21, 2017
GlobalFoundries will have the smaller cell, but Intel will still have about ~13.8-19.6% better logic density, (published estimates)Intel's ~102.9-103 MTr/mm² to GoFlo's ~86-90.5 MTr/mm², because Intel is using contact over active gate. Intel reports 100.8 MTr/mm² for their own process making it only about 11% logic density gap compared to Scotten Jones estimate of 90.5MTr/mm². That being said, GlobalFoundries have made significant improvements to their transistors! And they will be on as close to level playing field that we have seen, and will end up being a contest mainly between who has the best design.
IEDM 2017: Intel’s 10nm Platform Process
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By Dick James
Contact over active gate
The dummy gates at the cell boundaries have gone, replaced by a single gate spacing; and the gate contact is now over the active gate, ending the need for isolation space to fit in the contact.
The 14-nm process had a dummy gate at the edge of each cell, on the end of adjacent fins, similar to this image of a 22-nm device;
The 10-nm cell uses a dummy gate spacing between fin ends, which saves a gate pitch when packing two cells together, a claimed 20% cell area saving.
In actual fact there is no dummy gate in the finished product, just the fin etched where a single dummy gate would be. This was shown in the presentation, but it is not in the paper, but Samsung did something very similar in their 10-nm offering:
In fact, a dummy polySi gate is used, allowing source/drain formation without risking the fin edge; but for these particular gates the polySi removal etch goes a bit further, and etches the fin to separate the cells.
The second layout change is to shift the gate contact into the active transistor area, over the functional part of the gate (see below).
Such tight alignment with the source/drain (diffusion) contacts requires the development of self-aligned contacts to the gate, and modification of the self-aligned diffusion contacts that were already in use at 14-nm and 22-nm.
Diffusion contacts (left) and gate contacts
To do this, two etch-stop materials and two selective etches are used. After gate formation it is etched back and the cavity is filled with silicon nitride, as in earlier generations; the contact is then put in and also etched back, and the cavity is filled with silicon carbide. Then there is a selective etch to open the gate contact, which does not touch the SiC in the contact cavity, and a second selective etch removes the SiC from the contact cavity, but does not affect the gate contact periphery. Clearly this sequence is reliant on excellent etch selectivity between the different materials.