Intel's Future Chips: News, Rumours & Reviews

[logainofhades]

Laptop ram is easy to find. Also apparently Asrock did make a board like I was talking about.

http://www.tomsitpro.com/articles/mini-itx-server-motherboards-asrock-rack-lga2011-3,1-2561.html

 

[Gon Freecss]

I just found some Intel roadmaps!

Also, it's pretty interesting that Cascade Lake has added the VNNI instruction as the Skylake core doesn't support it. Maybe backported Cannonlake? Very interesting!

 

[Darkbreeze]

@goldstone77 30% performance improvement won't get you to 5GHz..

1800X freq is 3.6 GHz base - 4 GHz turbo.
Not that i expect those frequencies (specially base), but .... 30% extra means 4.7 GHz base - 5.2 GHz turbo

You are confusing "performance" with "clockspeed".

Performance = IPC * Clock * Number of Cores

The ways AMD can gain 30% performance improvements range from increasing Clock, increasing singe core performance though IPC gains, adding more cores, or a combination of the three. It's very unlikely any performance gains will be 100% clock.

Case in point, moving from 8 cores base to 10 cores base gets you 25% gains right there. So it wouldn't be terribly hard to reach 30% performance gains, best case, without even touching the clock.

In other news: Better then expected results leads Intel to a 4.5% stock gain. And Intel plans to have chips that address Specter/Meltdown out in Q4 2018.

https://www.slashgear.com/intel-spectre-and-meltdown-proof-cpus-coming-this-year-25517122/

This is ONLY true if the software and operating system are capable of USING those additional cores to your advantage. Currently, with some notable exceptions on high end applications, the majority of applications and even the OS itself becomes "core saturated" if you will, at some point. Helpful if you are simultaneously running MANY things in a multitasking environment, not so helpful if you are running one thing that is only optimized to take advantage of four thread processes.

IPC and clock speed are STILL to this day more likely to net you a performance increase in 75% of games and applications on a desktop environment once you get go beyond six or eight cores. Adding more cores to a system that is currently sitting idle on two of them 80% of the time isn't very helpful.

 

[gamerk316]

This is ONLY true if the software and operating system are capable of USING those additional cores to your advantage. Currently, with some notable exceptions on high end applications, the majority of applications and even the OS itself becomes "core saturated" if you will, at some point. Helpful if you are simultaneously running MANY things in a multitasking environment, not so helpful if you are running one thing that is only optimized to take advantage of four thread processes.

IPC and clock speed are STILL to this day more likely to net you a performance increase in 75% of games and applications on a desktop environment once you get go beyond six or eight cores. Adding more cores to a system that is currently sitting idle on two of them 80% of the time isn't very helpful.

And that's why in every other reply I've made in the past, I put the disclaimer "if all cores are loaded to 100%". Yes, cores that aren't being used contribute nothing; that's been my main argument in favor of clock/IPC since the Bulldozer days.

 

[Darkbreeze]

See what I did with your quote? ALL of you need to start doing this. The multiple embedded quotes that take up half a page need to stop. It is unnecessary and distracting to have four different quotes inside one quote and it distracts from the flow of the thread. This applies to ALL threads, not just this one. If it is somehow necessary, and I don't see that it is, ever, to quote multiple people, do it with separate individual quotes, not five of them embedded in one quote block.

Usually, this is a couple of other users doing this and they have been privately asked to stop doing it on multiple occasions. I do not mean to pick specifically on you, but it needs to be addressed and this was a good occasion to do it. Mostly we see this in this thread, and the Spectre/Meltdown thread, but it happens elsewhere too. If you are doing it, and you know who you are, please take the time to remove the unnecessary portions of any quote block in the future when posting.

It's aggravating and we should not have to come behind you guys and clean up your mess because you've been too lazy to remove the irrelevant parts yourself. That is all. Thanks.

 

[goldstone77]

See what I did with your quote?

Spoiler

ALL of you need to start doing this. The multiple embedded quotes that take up half a page need to stop. It is unnecessary and distracting to have four different quotes inside one quote and it distracts from the flow of the thread. This applies to ALL threads, not just this one. If it is somehow necessary, and I don't see that it is, ever, to quote multiple people, do it with separate individual quotes, not five of them embedded in one quote block.

Usually, this is a couple of other users doing this and they have been privately asked to stop doing it on multiple occasions. I do not mean to pick specifically on you, but it needs to be addressed and this was a good occasion to do it. Mostly we see this in this thread, and the Spectre/Meltdown thread, but it happens elsewhere too. If you are doing it, and you know who you are, please take the time to remove the unnecessary portions of any quote block in the future when posting.

It's aggravating and we should not have to come behind you guys and clean up your mess because you've been too lazy to remove the irrelevant parts yourself. That is all. Thanks.

Also, if you want to keep some previous statements for context of what you are talking about "Spoiler" works great! Left click and highlight the area you want to hide than click the "Spoiler" button to the right of the "Quote" button on the menu underneath the Label "Your solution" when you click Reply to <name>.

 

[manleysteele]

I'm pretty firmly in wait for Ice Lake mode. Once the general desktop SKU's drop, I'll look at the entire set of available processor/motherboards. I may buy and I may not. I'll also be taking a close look at AMD that is available at that time. Unless there is a huge change in games between now and then, I frankly don't need a new CPU.

 

[juanrga]

Spoiler doesn't work in mobile to me. All spoiled content is visible and scrolling those long posts is a pain in mobile

 

[Darkbreeze]

Mobile doesn't work much at all. I recommend not using it. For those that have to, if you cannot edit the quotes to your satisfaction, just don't quote. Or just add a note that it's in response to so and so's comment. Using mobile is not an excuse to avoid using best practices when posting. Most of us have learned that the mobile version of the site is useless and do not use it anymore.

 

[Isaiah4110]

Thank you darkbreeze!

 

[Darkbreeze]

Of course.

 

[8350rocks]

Mobile doesn't work much at all. I recommend not using it. For those that have to, if you cannot edit the quotes to your satisfaction, just don't quote. Or just add a note that it's in response to so and so's comment. Using mobile is not an excuse to avoid using best practices when posting. Most of us have learned that the mobile version of the site is useless and do not use it anymore.

Sadly, this is true...the mobile site version is garbage, and trying to run PC version on a mobile phone is an exercise in frustration.

Hopefully they do something about that at some point...

 

[goldstone77]

Are Intel 8th gen Core Reviews Accurate? Exploring Cooling Performance
Hardware Unboxed
Published on Feb 14, 2018
[video="https://www.youtube.com/watch?v=rJW4jRhwZBg"][/video]
https://www.youtube.com/watch?v=rJW4jRhwZBg
Great video, it explains the low base clocks, AVX2, and what to expect between Intel supplied coolers, budget air, and liquid coolers. The differences, based on workloads, are not bad at all performance wise, but you will encounter higher temps and throttling.

 

[goldstone77]

SiSoftware Official Live Ranker
Details for Result ID Intel(R) UHD Graphics, Gen11 LP ci-main-68861 (384SP 48C 600MHz, 768kB L2, 6GB) (OpenCL)
http://ranker.sisoftware.net/show_run.php?q=c2ffcdf4d2b3d2efdbedddeddceec8ba87b791f491ac9cbac9f4cc&l=en

 

[goldstone77]

IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects
David SchorIEDM 2017, ISSCC 2018, Process TechnologiesFebruary 17, 2018
https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-intels-10nm-switching-to-cobalt-interconnects/

Overview
The major features are:

2.7x density over their 14nm
3rd generation FinFET transistors
Self-Aligned Quad-Patterning (SAQP)
Contact-over-active-gate (COAG)
Cobalt local interconnect, vias, and trench contacts
Cobalt interconnect liners

Design Features
Intel’s 10 nanometer largely builds on many of their existing technologies.

2nd generation Low-κ spacer
3rd generation of fully depleted FinFET transistors
5th generation High-κ metal gate
7th generation strain silicon
Self-Aligned Quad Patterning (SAQP) for the critical patterning layers (3 critical layers)
4 workfunction metals on the base process
Self-Aligned trench contact

Spoiler

t’s worth pointing out that despite its name, in practice there’s just the etched line spacing and not an actual dummy gate. The TEM below from ISSCC 2018 shows it clearly.

Contact Over Active Gate (COAG)
The second feature Intel has introduced is the contact over active gate (COAG). Traditionally, as shown below with the single transistor, you extend the gate over the isolation and then drop the gate via over the gate. What Intel has done with their 10nm process is allow the gate via to be dropped directly over the active area which allows for further reduction of the cell height. Intel reported a cell reduction of 10% by using COAG.

Spoiler

This is a pretty complex change which involves using a self-aligned contacts process for the diffusion contact and gate contact. Intel has been using self-aligned diffusion contacts since their 22nm node to form tight contact to gate overlays so this is another flow extension. This is done by recess filling and polishing the gate back to leave the silicon nitride etch-stop material in the cavity to prevent the diffusion contact from shorting the gate.

Spoiler

Self-Aligned Diffusion
For this 10nm technology, they extended the flow with an additional recess of the diffusion contact and the deposition of a silicon carbide etch-stop layer to prevent the gate contact from shorting the diffusion contact. Since the underlying material remains unharmed, both the diffusion and gate vias shows excellent selectivity. Overall, this adds three additional steps – one etch, one dep, and one polish, but it allows the gate contacts to land on the active area itself.

Spoiler

Final Thoughts
The monumental engineering feat Intel has presented at IEDM 2017 can only be described as a highly advanced 7nm-class manufacturing technology. Interestingly, if they ramp-up by around mid-year, they will still manage to squeak by and maintain 7x density in roughly 7 years in their relentless pursuit to keep Moore’s Law going. So far it has worked and while Moore’s Law is still alive, it’s becoming ever more difficult to pursue.

Unfortunately, this isn’t being done in a vacuum and while their 10nm was initially supposed to ramp-up in late 2016, it has since shifted to 2018. During that time, their competition such as TSMC has managed to release their 10nm process.

Spoiler

Intel’s 10nm vs Foundries 10nm (Source: Intel)
Both TSMC and Samsung 10 nanometer nodes are more comparable to Intel’s 14nm, however, Intel’s 10nm delays which has lasted throughout 2017 has meant that their competitors have managed to further narrow the gap dramatically. TSMC will ramp-up their 7nm production sometimes later this year and GlobalFoundries will follow sometimes in late 2019. Unlike foundry 10nm nodes, their 7nm nodes are in fact more or less comparable to Intel’s 10nm in terms of density. While Intel still leads with various advances to the wiring such as the aggressively scaled cobalt local interconnections, they no longer have a multi-year density lead.

2019 will be the first time in a fairly long time that all four leading-edge foundries (Intel, Samsung, TSMC, and GlobalFoundries) will be on an even playing field. Ultimately it’s not our analysis, but the final products, that will demonstratively prove what those process technologies have to offer and who is leading the semiconductor industry.

 

[YoAndy]

See what I did with your quote? ALL of you need to start doing this. The multiple embedded quotes that take up half a page need to stop. It is unnecessary and distracting to have four different quotes inside one quote and it distracts from the flow of the thread. This applies to ALL threads, not just this one. If it is somehow necessary, and I don't see that it is, ever, to quote multiple people, do it with separate individual quotes, not five of them embedded in one quote block.

Usually, this is a couple of other users doing this and they have been privately asked to stop doing it on multiple occasions. I do not mean to pick specifically on you, but it needs to be addressed and this was a good occasion to do it. Mostly we see this in this thread, and the Spectre/Meltdown thread, but it happens elsewhere too. If you are doing it, and you know who you are, please take the time to remove the unnecessary portions of any quote block in the future when posting.

It's aggravating and we should not have to come behind you guys and clean up your mess because you've been too lazy to remove the irrelevant parts yourself. That is all. Thanks.

I agree with you, first time been actually asked to insert spoiler. It is a bit tricky when using a mobile device I haven't been able to do it while using my phone. Do you know about any procedure on how to?

 

[gamerk316]

I agree with you, first time been actually asked to insert spoiler. It is a bit tricky when using a mobile device I haven't been able to do it while using my phone. Do you know about any procedure on how to?

Consider me old school:

[ spoiler ] and [ /spoiler ] without the spaces.

 

[goldstone77]

HAHAHA! Thanks for that gamerk316!

 

[YoAndy]

Works easy on my computer but my phone is another story lol

 

[juanrga]

As stated above spoiler tags don't work on mobile for me. People can add spoiler tags to long chunks of text, but I continue seing all the spoiled text in my phone as normal text.

 

[8350rocks]

https://www.fool.com/investing/2018/02/19/intel-admits-that-its-10-nano-technology-is-behind.aspx

Update regarding 10nm from an engineer talk.

 

[juanrga]

https://www.fool.com/investing/2018/02/19/intel-admits-that-its-10-nano-technology-is-behind.aspx

Update regarding 10nm from an engineer talk.

There is not any update. SRAM densities have been known since past year and it has been reported that Intel 10nm has slightly larger SRAM cell densities than competing 7nm nodes. On the other hand Intel 10nm has a density lead in logic over competitors 7nm

This is all explained in the excellent summary by Wikichip, which is posted a pair of posts above in this same page.

 

[goldstone77]

Retailer Leaks Three Upcoming Coffee Lake CPUs
by Leon Chan February 20, 2018 at 12:00 PM
http://www.tomshardware.com/news/retailer-leaks-coffee-lake-cpus,36551.html

Follow the article link for more details, but numbers like 350 GHz are 3.5GHz etc.

 

[aldaia]

There is not any update. SRAM densities have been known since past year and it has been reported that Intel 10nm has slightly larger SRAM cell densities than competing 7nm nodes. On the other hand Intel 10nm has a density lead in logic over competitors 7nm

Bolded part is wrong, Intel 10 nm dosn't have larger SRAM cell densities than 7nm. i is the other way around. 7nm has denser SRAM than intel 10 nm. To be more precise, GloFo 7nm HD cell is 15 % denser than intel 10nm HD cell and 7nm HP cell is 25% denser than intel 10 nm HP cell.

 

[YoAndy]

Intel Announces Discrete GPU Prototype
Intel's GPU core consists of a vector core called "EU (Execution Unit)". One EU has two 4-way vector units. FP32 (32-bit floating point arithmetic) unit is 4-way, 128-bit long vector unit. The EU includes two vector units and 7 multithreaded general purpose registers (GRF), instruction fetchers and branch units.

In the prototype chip, six EUs are bound and constitute "Sub-Slice (SS: sub slice)". In addition to the EU, samplers (texture units), L1 / L2 caches, thread dispatchers, data ports, etc. are attached to the sub slices.

In this chip, it seems that three sub slices constitute one "Slice". Three EUs from SS 0 to SS 2 can be seen in the die picture. Of the three EU sub-slices, the new power control mechanism of this time is implemented in two. SS1 and SS2 are newly designed EU.

SS0 is designed as usual for comparison. A slice composed of three SSs is a full-function GPU core, and includes a graphics fixed function (FF: Fixed Function), a command streamer, an L3 cache, and the like.

The test chip has 1 slice configuration, and it carries 3 sub slices in total, 18 EUs. The product summation unit of the FP32 (32-bit floating point operation) in the vector unit is a calculation of 144 units in total. The low-end GT 1 of Intel graphics for PC is 96 FP 32 in standard implementation.

Because the test chip is 144 units with low frequency LP implementation, roughly speaking it can say that it is a graphics level performance for low end PC. Also, a normal GPU core comes with a multimedia core including a moving picture codec etc. However, it is not specified whether it is contained in this prototype chip or not.

The GPU chip announced at ISSCC includes not only the GPU core but also a system agent (SA: system agent) including a control system and around I / O. The memory interface is the host side. For that reason, the SA also has a large paging cache of 4 MB. It is connected to the host PC via the FPGA bridge. As far as the configuration is concerned, it is a prototype for demonstration experiments.

For more information and more graphs you can look here :https://translate.google.com/translate?depth=1&nv=1&rurl=translate.google.com&sp=nmt4&tl=en&u=https://pc.watch.impress.co.jp/docs/column/kaigai/1107078.html&xid=17259,15700021,15700105,15700122,15700124,15700149,15700168,15700173,15700201