goldstone77
Distinguished
YoAndy :
Intel Announces Discrete GPU Prototype
Intel's GPU core consists of a vector core called "EU (Execution Unit)". One EU has two 4-way vector units. FP32 (32-bit floating point arithmetic) unit is 4-way, 128-bit long vector unit. The EU includes two vector units and 7 multithreaded general purpose registers (GRF), instruction fetchers and branch units.
Intel's GPU core consists of a vector core called "EU (Execution Unit)". One EU has two 4-way vector units. FP32 (32-bit floating point arithmetic) unit is 4-way, 128-bit long vector unit. The EU includes two vector units and 7 multithreaded general purpose registers (GRF), instruction fetchers and branch units.
In the prototype chip, six EUs are bound and constitute "Sub-Slice (SS: sub slice)". In addition to the EU, samplers (texture units), L1 / L2 caches, thread dispatchers, data ports, etc. are attached to the sub slices.
In this chip, it seems that three sub slices constitute one "Slice". Three EUs from SS 0 to SS 2 can be seen in the die picture. Of the three EU sub-slices, the new power control mechanism of this time is implemented in two. SS1 and SS2 are newly designed EU.
SS0 is designed as usual for comparison. A slice composed of three SSs is a full-function GPU core, and includes a graphics fixed function (FF: Fixed Function), a command streamer, an L3 cache, and the like.
The test chip has 1 slice configuration, and it carries 3 sub slices in total, 18 EUs. The product summation unit of the FP32 (32-bit floating point operation) in the vector unit is a calculation of 144 units in total. The low-end GT 1 of Intel graphics for PC is 96 FP 32 in standard implementation.
Because the test chip is 144 units with low frequency LP implementation, roughly speaking it can say that it is a graphics level performance for low end PC. Also, a normal GPU core comes with a multimedia core including a moving picture codec etc. However, it is not specified whether it is contained in this prototype chip or not.
The GPU chip announced at ISSCC includes not only the GPU core but also a system agent (SA: system agent) including a control system and around I / O. The memory interface is the host side. For that reason, the SA also has a large paging cache of 4 MB. It is connected to the host PC via the FPGA bridge. As far as the configuration is concerned, it is a prototype for demonstration experiments.
For more information and more graphs you can look here :https://translate.google.com/translate?depth=1&nv=1&rurl=translate.google.com&sp=nmt4&tl=en&u=https://pc.watch.impress.co.jp/docs/column/kaigai/1107078.html&xid=17259,15700021,15700105,15700122,15700124,15700149,15700168,15700173,15700201
In this chip, it seems that three sub slices constitute one "Slice". Three EUs from SS 0 to SS 2 can be seen in the die picture. Of the three EU sub-slices, the new power control mechanism of this time is implemented in two. SS1 and SS2 are newly designed EU.
SS0 is designed as usual for comparison. A slice composed of three SSs is a full-function GPU core, and includes a graphics fixed function (FF: Fixed Function), a command streamer, an L3 cache, and the like.
The test chip has 1 slice configuration, and it carries 3 sub slices in total, 18 EUs. The product summation unit of the FP32 (32-bit floating point operation) in the vector unit is a calculation of 144 units in total. The low-end GT 1 of Intel graphics for PC is 96 FP 32 in standard implementation.
Because the test chip is 144 units with low frequency LP implementation, roughly speaking it can say that it is a graphics level performance for low end PC. Also, a normal GPU core comes with a multimedia core including a moving picture codec etc. However, it is not specified whether it is contained in this prototype chip or not.
The GPU chip announced at ISSCC includes not only the GPU core but also a system agent (SA: system agent) including a control system and around I / O. The memory interface is the host side. For that reason, the SA also has a large paging cache of 4 MB. It is connected to the host PC via the FPGA bridge. As far as the configuration is concerned, it is a prototype for demonstration experiments.
For more information and more graphs you can look here :https://translate.google.com/translate?depth=1&nv=1&rurl=translate.google.com&sp=nmt4&tl=en&u=https://pc.watch.impress.co.jp/docs/column/kaigai/1107078.html&xid=17259,15700021,15700105,15700122,15700124,15700149,15700168,15700173,15700201
However, the prototype chip of this time is not a level that can be put on the market as a product. It is a GPU chip for technical verification to the last. It is based on existing Intel 's built - in GPU architecture and examines power and performance control technology using integrated voltage regulator (IVR).
They are just using this for testing power, it's not a new design or anything special it is just being used to test voltages.
Edit: It's also mentioned here:
https://liliputing.com/2018/02/intel-unveils-discrete-gpu-prototype.htmlUpdate: It turns out Intel presented a paper describing a new power management technique for exiting GPU technology rather than a new discrete graphics solution, contrary to earlier reports. According to an Intel spokesperson:
Last week at ISSCC, Intel Labs presented a research paper exploring new circuit techniques optimized for power management. The team used an existing Intel integrated GPU architecture (Gen 9 GPU) as a proof of concept for these circuit techniques. This is a test vehicle only, not a future product. While we intend to compete in graphics products in the future, this research paper is unrelated. Our goal with this research is to explore possible, future circuit techniques that may improve the power and performance of Intel products.