Intel's Future Chips: News, Rumours & Reviews

[goldstone77]

Bloomfield: 4 cores
Westmere-EP: 6 cores
SandyBridge-E: 6 cores
IvyBridge-E: 6 cores
Haswell-E: 8 cores
Broadwell-E: 10 cores

It is not like if Intel has not added moar cores systematically since 45nm!!!!

That's true, but Intel was able to charge much more $$$ for those higher end HEDT platform processors as well, which had no real competition. Example: 6950X 10 core Recommended Customer Price $1723.00 - $1743.00
Per core cost for the consumer goes up ridiculously, because Intel didn't have competition and despite having reduced production cost for each advancement in process technology. They really had consumers bent over the barrel! Planning out the mainstream processor line to include more cores to show increased productivity benchmark scores, because you can't create new process technology seams like an answer for the inclusion of moar cores for the future generations to me. Just my opinion. They new about the manufacturing difficulties, and architects planned ahead, by adding cores to show performance gains over previous generations. I say this because historically each node brought greater performance benefits.

 

[-Fran-]

In related news: https://www.anandtech.com/show/12677/tsmc-kicks-off-volume-production-of-7nm-chips

So, Apple might get an edge over other CPU makers now (Samsung and Qualcomm mainly)? I would imagine they'll be the firsts to fill the 7nm lines from TSMC? With nVidia in close second?

And the obvious question to ask: does this mean Intel is now behind TSMC?

Cheers!

 

[goldstone77]

In related news: https://www.anandtech.com/show/12677/tsmc-kicks-off-volume-production-of-7nm-chips

So, Apple might get an edge over other CPU makers now (Samsung and Qualcomm mainly)? I would imagine they'll be the firsts to fill the 7nm lines from TSMC? With nVidia in close second?

And the obvious question to ask: does this mean Intel is now behind TSMC?

Cheers!

That is exactly what that means. TSMC is close to Intel's 10nm.

Also, Samsung as well with production using EUV in Jun:

The combination of what is known about EUV and the rumors about Samsung make me believe that we will in fact see Samsung begin to ship 7nm wafers using EUV starting in June. Likely this will be by running the EUV systems in a way that delivers low throughput and high costs and there may be yield issues as well, but this will make Samsung the first to enter production with EUV.

I will say the customer list surprises me, I thought Apple was at TSMC for 100% of their 7nm business and I thought Qualcomm and Xilinx were also TSMC 7nm customers. But the rest of this report is credible in my opinion.

https://www.semiwiki.com/forum/content/7403-samsung-starting-7nm-production-euv-june.html

Technically, Samsung adopting EUV first for volume production will give them an edge moving forward to smaller nodes.

 

[Gon Freecss]

In related news: https://www.anandtech.com/show/12677/tsmc-kicks-off-volume-production-of-7nm-chips

So, Apple might get an edge over other CPU makers now (Samsung and Qualcomm mainly)? I would imagine they'll be the firsts to fill the 7nm lines from TSMC? With nVidia in close second?

And the obvious question to ask: does this mean Intel is now behind TSMC?

Cheers!

Yeah, but they're still a long time from bringing the technology into the market. Their 7nm process lags quite a bit behind Intel's 10nm (especially 10nm+ and 10nm++), but it's close, and it's hitting the market in volume first. Intel will probably take the lead sooner after though.

 

[-Fran-]

True. Intel still has a lot money to throw at the problem and might still have an edge.

That being said, now the other foundries are so close that it might be making Intel really nervous. I wonder if we even can say that Intel is "ahead", given how close the manufacturers are now from each other. But well, we need to see how they perform first to draw better conclusions. Having volume productions though is a big milestone for TSMC and Intel will need to give an announcement soon. Investors might not be happy with this XD

Cheers!

 

[gamerk316]

True. Intel still has a lot money to throw at the problem and might still have an edge.

That being said, now the other foundries are so close that it might be making Intel really nervous. I wonder if we even can say that Intel is "ahead", given how close the manufacturers are now from each other. But well, we need to see how they perform first to draw better conclusions. Having volume productions though is a big milestone for TSMC and Intel will need to give an announcement soon. Investors might not be happy with this XD

Cheers!

This all goes back to a point I made not long ago: Given that die shrinks are going to get more difficult (expensive) going forward, I would not automatically assume farther die shrinks will be a thing for consumer grade chips going forward. I could easily see a case where the next shrink is simply too expensive for companies to bother using it unless there is a clear need to do so.

As for core count, Intel has to increase it now for no other reason then the above; free performance gains via die shrinks is near its end, so Intel has to do SOMETHING to increase performance. And adding cores is the easiest way to do so, even if that performance isn't uniform across the board.

 

[Gon Freecss]

True. Intel still has a lot money to throw at the problem and might still have an edge.

That being said, now the other foundries are so close that it might be making Intel really nervous. I wonder if we even can say that Intel is "ahead", given how close the manufacturers are now from each other. But well, we need to see how they perform first to draw better conclusions. Having volume productions though is a big milestone for TSMC and Intel will need to give an announcement soon. Investors might not be happy with this XD

Cheers!

This all goes back to a point I made not long ago: Given that die shrinks are going to get more difficult (expensive) going forward, I would not automatically assume farther die shrinks will be a thing for consumer grade chips going forward. I could easily see a case where the next shrink is simply too expensive for companies to bother using it unless there is a clear need to do so.

As for core count, Intel has to increase it now for no other reason then the above; free performance gains via die shrinks is near its end, so Intel has to do SOMETHING to increase performance. And adding cores is the easiest way to do so, even if that performance isn't uniform across the board.

Die shrinks don't give you any direct performance increases. It only gives you more density which you can use to reduce die sizes and increase profit.

 

[goldstone77]

ASML: Arms Dealer in Epic Battle of Taiwan Semi vs. Samsung, Says Credit Suisse
ByTiernan Ray Updated April 9, 2018 12:33 p.m. ET

Chip equipment vendor ASML Holding (ASML) is doing better than most think, as its cutting-edge chip-making equipment is a key armament in the battle for supremacy between contract chipmaker Taiwan Semiconductor Manufacturing (TSM) and competitor Samsung Electronics (005930KS), writes Credit Suisse’s Farhan Ahmad this morning.

Ahmad, who upgraded ASML stock to Outperform back in mid-January, thinks investors are wringing their hands about slowing equipment orders for ASML that are not actually the case.

He writes, “there has been recent noise suggesting that there could be pushouts of EUV tools at TSMC,” referring to the company’s machines that direct beams of “extreme ultraviolet,” or EUV, light to etch circuits in silicon.

"Our checks, however, suggest that rather than weakening, the outlook for EUV has strengthened,” writes Ahmad. “And ASML is on track to be completely booked out for 2019 EUV production capacity."

He notes that Taiwan Semi "placed orders of ~$1bn with ASML and Lasertec on Apr 2” and adds that "we see strong possibility that this may show up as orders for 6-8 tools in Q1."

Behind Taiwan Semi’s need to buy the machines is an aggressive push by Samsung for the new equipment:

Samsung is continuing to be the most aggressive on EUV. Recent checks suggest that in addition to 7nm, the The company may adopt EUV for at least part of production on 1y nm DRAM (~1 layer), and DRAM production could actually come earlier than 7nm Foundry/Logic as Samsung plans to uses less risky DRAM to prepare for broad adoption of EUV at 7nm production. Samsung is marketing design flexibility, shorter cycle times, and smaller dies as differentiators on 7nm Foundry. The company is building a dedicated EUV fab to be shared between DRAM and Logic with capacity of 38 EUV tools.

He thinks Taiwan Semi “may need to accelerate their 5nm to ensure they stay competitive with Samsung,” referring to chips made with their smallest feature measuring 5 nanometers, or billionths of an inch.

5-nano, as it’s known, is the real primetime for Taiwan Semi with ASML’s EUV, he writes:

There have been reports out of Taiwan that 7nm+ interest from TSMC customers is low. This is understandable as 7nm+ was not expected to offer the design flexibility that is associated with EUV single patterning and EUV was expected to be used for only cut mask as vias (no change in design needed). 7nm+ was expected to be primarily a node to wrinkle out the challenges associated with EUV adoption, ahead of the broader adoption of EUV at the 5nm node (true 7nm node). We have been consistent in stating that 7nm+ adoption is likely to be limited to few layers and to only a portion of capacity. We expect TSMC to start production on 7nm+ by early 2019, and prepare for volume production of 5nm in 2020. In order to meet the production capacity requirement, the the company will need to start installing tools in 2019. We believe the recent tool orders are from TSMC are an indication that the the company is trying to step up its plans for 5nm.

https://www.barrons.com/articles/asml-arms-dealer-in-epic-battle-of-taiwan-semi-vs-samsung-says-credit-suisse-1523291624

Samsung and TSMC are the two fighting for process lead. Samsung is noted as being the most aggressive with EUV, which is the only way to 5nm and smaller.
Edit: EUV is the only cost effective way to 5nm!

 

[goldstone77]

Beyond 7nm – the race to 4nm is Samsung’s to lose
BY ROBERT TRIGGSNOVEMBER 16, 2017

https://www.androidauthority.com/4nm-processing-node-812959/

 

[goldstone77]

True. Intel still has a lot money to throw at the problem and might still have an edge.

That being said, now the other foundries are so close that it might be making Intel really nervous. I wonder if we even can say that Intel is "ahead", given how close the manufacturers are now from each other. But well, we need to see how they perform first to draw better conclusions. Having volume productions though is a big milestone for TSMC and Intel will need to give an announcement soon. Investors might not be happy with this XD

Cheers!

This all goes back to a point I made not long ago: Given that die shrinks are going to get more difficult (expensive) going forward, I would not automatically assume farther die shrinks will be a thing for consumer grade chips going forward. I could easily see a case where the next shrink is simply too expensive for companies to bother using it unless there is a clear need to do so.

As for core count, Intel has to increase it now for no other reason then the above; free performance gains via die shrinks is near its end, so Intel has to do SOMETHING to increase performance. And adding cores is the easiest way to do so, even if that performance isn't uniform across the board.

Die shrinks don't give you any direct performance increases. It only gives you more density which you can use to reduce die sizes and increase profit.

That's an interesting statement, since every node shrink offers better performance and less power consumption.

 

[Gon Freecss]

True. Intel still has a lot money to throw at the problem and might still have an edge.

That being said, now the other foundries are so close that it might be making Intel really nervous. I wonder if we even can say that Intel is "ahead", given how close the manufacturers are now from each other. But well, we need to see how they perform first to draw better conclusions. Having volume productions though is a big milestone for TSMC and Intel will need to give an announcement soon. Investors might not be happy with this XD

Cheers!

This all goes back to a point I made not long ago: Given that die shrinks are going to get more difficult (expensive) going forward, I would not automatically assume farther die shrinks will be a thing for consumer grade chips going forward. I could easily see a case where the next shrink is simply too expensive for companies to bother using it unless there is a clear need to do so.

As for core count, Intel has to increase it now for no other reason then the above; free performance gains via die shrinks is near its end, so Intel has to do SOMETHING to increase performance. And adding cores is the easiest way to do so, even if that performance isn't uniform across the board.

Die shrinks don't give you any direct performance increases. It only gives you more density which you can use to reduce die sizes and increase profit.

That's an interesting statement, since every node shrink offers better performance and less power consumption.

Source?

 

[goldstone77]

That's an interesting statement, since every node shrink offers better performance and less power consumption.

Source?

Die shrinks are the key to improving price/performance at semiconductor companies such as Intel, AMD (including the former ATI), NVIDIA, and Samsung. Examples in the 2000s include the codenamed Cedar Mill Pentium 4 processors (from 90 nm CMOS to 65 nm CMOS) and Penryn Core 2 processors (from 65 nm CMOS to 45 nm CMOS), the codenamed Brisbane Athlon 64 X2 processors (from 90 nm SOI to 65 nm SOI), and various generations of GPUs from both ATI and NVIDIA. In January 2010, Intel released Clarkdale Core i5 and Core i7 processors fabricated with a 32 nm process, down from a previous 45 nm process used in older iterations of the Nehalem processor microarchitecture. Intel, in particular, formerly focused on leveraging die shrinks to improve product performance at a regular cadence through its Tick-Tock model. In this business model, every new microarchitecture (tick) is followed by a die shrink (tock) to improve performance with the same microarchitecture.[1]

Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased clock rate headroom, and lower prices.[1] Since the cost to fabricate a 200-mm or 300-mm silicon wafer is proportional to the number of fabrication steps, and not proportional to the number of chips on the wafer, die shrinks cram more chips onto each wafer, resulting in lowered manufacturing costs per chip.

Die shrink
https://en.wikipedia.org/wiki/Die_shrink

 

[gamerk316]

True. Intel still has a lot money to throw at the problem and might still have an edge.

That being said, now the other foundries are so close that it might be making Intel really nervous. I wonder if we even can say that Intel is "ahead", given how close the manufacturers are now from each other. But well, we need to see how they perform first to draw better conclusions. Having volume productions though is a big milestone for TSMC and Intel will need to give an announcement soon. Investors might not be happy with this XD

Cheers!

This all goes back to a point I made not long ago: Given that die shrinks are going to get more difficult (expensive) going forward, I would not automatically assume farther die shrinks will be a thing for consumer grade chips going forward. I could easily see a case where the next shrink is simply too expensive for companies to bother using it unless there is a clear need to do so.

As for core count, Intel has to increase it now for no other reason then the above; free performance gains via die shrinks is near its end, so Intel has to do SOMETHING to increase performance. And adding cores is the easiest way to do so, even if that performance isn't uniform across the board.

Die shrinks don't give you any direct performance increases. It only gives you more density which you can use to reduce die sizes and increase profit.

More density = more transistors = more performance.

 

[goldstone77]

More density = more transistors = more performance.

every new microarchitecture (tick) is followed by a die shrink (tock) to improve performance with the same microarchitecture.[1]

Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased clock rate headroom, and lower prices.

You don't have to add more transistors to increase performance from a die shrink, performance is extracted from the reduction in current/power consumption.

Edit: The 2000 series Ryzen processors show this property over first generation.

 

[Gon Freecss]

That's an interesting statement, since every node shrink offers better performance and less power consumption.

Source?

Die shrinks are the key to improving price/performance at semiconductor companies such as Intel, AMD (including the former ATI), NVIDIA, and Samsung. Examples in the 2000s include the codenamed Cedar Mill Pentium 4 processors (from 90 nm CMOS to 65 nm CMOS) and Penryn Core 2 processors (from 65 nm CMOS to 45 nm CMOS), the codenamed Brisbane Athlon 64 X2 processors (from 90 nm SOI to 65 nm SOI), and various generations of GPUs from both ATI and NVIDIA. In January 2010, Intel released Clarkdale Core i5 and Core i7 processors fabricated with a 32 nm process, down from a previous 45 nm process used in older iterations of the Nehalem processor microarchitecture. Intel, in particular, formerly focused on leveraging die shrinks to improve product performance at a regular cadence through its Tick-Tock model. In this business model, every new microarchitecture (tick) is followed by a die shrink (tock) to improve performance with the same microarchitecture.[1]

Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased clock rate headroom, and lower prices.[1] Since the cost to fabricate a 200-mm or 300-mm silicon wafer is proportional to the number of fabrication steps, and not proportional to the number of chips on the wafer, die shrinks cram more chips onto each wafer, resulting in lowered manufacturing costs per chip.

Die shrink
Nothing]https://en.wikipedia.org/wiki/Die_shrink

Nothing above says die shrink directly gives you more performance.

True. Intel still has a lot money to throw at the problem and might still have an edge.

That being said, now the other foundries are so close that it might be making Intel really nervous. I wonder if we even can say that Intel is "ahead", given how close the manufacturers are now from each other. But well, we need to see how they perform first to draw better conclusions. Having volume productions though is a big milestone for TSMC and Intel will need to give an announcement soon. Investors might not be happy with this XD

Cheers!

This all goes back to a point I made not long ago: Given that die shrinks are going to get more difficult (expensive) going forward, I would not automatically assume farther die shrinks will be a thing for consumer grade chips going forward. I could easily see a case where the next shrink is simply too expensive for companies to bother using it unless there is a clear need to do so.

As for core count, Intel has to increase it now for no other reason then the above; free performance gains via die shrinks is near its end, so Intel has to do SOMETHING to increase performance. And adding cores is the easiest way to do so, even if that performance isn't uniform across the board.

Die shrinks don't give you any direct performance increases. It only gives you more density which you can use to reduce die sizes and increase profit.

More density = more transistors = more performance.

And more transistors doesn't directly give you more performance in CPUs.

More density = more transistors = more performance.

every new microarchitecture (tick) is followed by a die shrink (tock) to improve performance with the same microarchitecture.[1]

Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased clock rate headroom, and lower prices.

You don't have to add more transistors to increase performance from a die shrink, performance is extracted from the reduction in current/power consumption.

Edit: The 2000 series Ryzen processors show this property over first generation.

Wrong. Intel's 32nm clocked around as high as their 14nm process with Sandy Bridge and Skylake (Sandy Bridge actually clocked a bit higher). You don't gain more performance with more density and transistors. Architecture is what gives you more performance.

This is different in GPUs, but I digress.

 

[-Fran-]

Uhm... Strictly speaking, if you want to port a "carbon copy" of the design from one process to the other (let's just say it's possible, lol), then you would have explicitly different thermal behaviors that will affect Turbos (for example) and power consumption would be lowered (provided the voltage requirement lowers).

Unfortunately, in the real world of CPU making, you can't do the "carbon copies" of the designs. You have to adapt voltage regulators (changing your thermal profile a bit) and transistor performance also changes, so you need to adjust timings across the design.

To quote Sinatra:
"Love and marriage, love and marriage
They go together like a horse and carriage
This I tell you, brother
You can't have one without the other"

Cheers!

 

[goldstone77]

every new microarchitecture (tick) is followed by a die shrink (tock) to improve performance with the same microarchitecture.[1]

Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased clock rate headroom, and lower prices.

You don't have to add more transistors to increase performance from a die shrink, performance is extracted from the reduction in current/power consumption.

Edit: The 2000 series Ryzen processors show this property over first generation.

Wrong. Intel's 32nm clocked around as high as their 14nm process with Sandy Bridge and Skylake (Sandy Bridge actually clocked a bit higher). You don't gain more performance with more density and transistors. Architecture is what gives you more performance.

This is different in GPUs, but I digress.

If you disagree with the wiki and the references it uses, submit a change with references to prove your points!

Intel, in particular, formerly focused on leveraging die shrinks to improve product performance at a regular cadence through its Tick-Tock model. In this business model, every new microarchitecture (tick) is followed by a die shrink (tock) to improve performance with the same microarchitecture.[1]

Die shrink
https://en.wikipedia.org/wiki/Die_shrink

 

[Gon Freecss]

every new microarchitecture (tick) is followed by a die shrink (tock) to improve performance with the same microarchitecture.[1]

Die shrinks are beneficial to end-users as shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production), increased clock rate headroom, and lower prices.

You don't have to add more transistors to increase performance from a die shrink, performance is extracted from the reduction in current/power consumption.

Edit: The 2000 series Ryzen processors show this property over first generation.

Wrong. Intel's 32nm clocked around as high as their 14nm process with Sandy Bridge and Skylake (Sandy Bridge actually clocked a bit higher). You don't gain more performance with more density and transistors. Architecture is what gives you more performance.

This is different in GPUs, but I digress.

If you disagree with the wiki and the references it uses, submit a change with references to prove your points!

Intel, in particular, formerly focused on leveraging die shrinks to improve product performance at a regular cadence through its Tick-Tock model. In this business model, every new microarchitecture (tick) is followed by a die shrink (tock) to improve performance with the same microarchitecture.[1]

Die shrink
https://en.wikipedia.org/wiki/Die_shrink

Again, die shrinks do not directly improve performance. They do, but indirectly. Also, in Intel die shrink architectures, the architecture itself gets improved and changed. That's why they gain IPC. Die shrinks can help in increasing clock speeds, but that's up to the architecture too.

 

[goldstone77]

Intel Corp. Wants to Build a "Revolutionary" Processor Core
Say hello to Intel's Ocean Cove processor core.
Ashraf Eassa (TMFChipFool) Apr 25, 2018 at 6:18PM

According to job listings on the company's website, Intel seems to be ramping up hiring for a major new processor core project, known as "Ocean Cove." Let's dive into the details.

https://www.fool.com/investing/2018/04/25/intel-corp-wants-to-build-a-revolutionary-processo.aspx

Also today Tesla Announced:
Tesla’s VP of Autopilot and chip guru Jim Keller is leaving, another former Apple chip designer is tapped Fred Lambert - Apr. 25th 2018 10:23 pm ET

Today is Jim Keller’s last day at Tesla, where he has overseen low-voltage hardware, Autopilot software and infotainment. Prior to joining Tesla, Jim’s core passion was microprocessor engineering and he’s now joining a company where he’ll be able to once again focus on this exclusively. We appreciate his contributions to Tesla and wish him the best.

A source says that the chipmaker in question is Intel. Keller previously worked at AMD and Apple’s PA Semi.

https://electrek.co/2018/04/25/tesla-autopilot-jim-keller-leaving-chip/amp/

And you can guess what the rumor is! Intel!

Edit: It's confirmed Jim Keller is working for Intel!

 

[-Fran-]

That is actually interesting. So Intel is getting desperate enough to do that.

It's a good time to be a decent engy with a CPU-related background 😛

Cheers!

 

[gamerk316]

To me, it sounds like Intel is finally moving on from the architecture it's been using since Sandy Bridge. I think the combination of the inability to squeeze any additional performance out of the core combined with the security problems that are starting to be uncovered both played a part in that decision.

Based on the way the article is written, it *sounds* like Intel is sticking with x86-64 and not moving on to a new instruction set, which makes sense but limits a bit of what they can do with the underlying architecture. We'll see I guess.

I'm not terribly surprised Intels working on a brand new core design; this has been a bit overdue to be honest.

 

[goldstone77]

I think Intel they realized how powerful Zen core really is, and they are worried about 7nm Zen 2! They need something to put them ahead, and there is only 1 guy that can beat his own designs! This guy has consistently designed processor architecture that has stomped Intel's army of engineers. He is obviously the best there is!

 

[goldstone77]

Jim Keller Joins Intel to Lead Silicon Engineering

ANTA CLARA, Calif., April 26, 2018 – Intel today announced that Jim Keller will join Intel as a senior vice president. He will lead the company’s silicon engineering, which encompasses system-on-chip (SoC) development and integration.
“Jim is one of the most respected microarchitecture design visionaries in the industry, and the latest example of top technical talent to join Intel,” said Dr. Murthy Renduchintala, Intel’s chief engineering officer and group president of the Technology, Systems Architecture & Client Group (TSCG). “We have embarked on exciting initiatives to fundamentally change the way we build the silicon as we enter the world of heterogeneous process and architectures. Jim joining us will help accelerate this transformation.”

Keller brings to Intel more than 20 years of experience in x86 and ARM-based microarchitecture design across a broad range of platforms, including PCs, servers, mobile devices and cars.

“I had a great experience working at Tesla, learned a lot, and look forward to all the great technology coming from Tesla in the future. My lifelong passion has been developing the world’s best silicon products,” Keller said. “The world will be a very different place in the next decade as a result of where computing is headed. I am excited to join the Intel team to build the future of CPUs, GPUs, accelerators and other products for the data-centric computing era.”

Keller, 59, joins Intel from Tesla, where he most recently served as vice president of Autopilot and Low Voltage Hardware. Prior to Tesla, he served as corporate vice president and chief cores architect at AMD, where he led the development of the Zen* architecture. Previously, Keller was vice president of Engineering and chief architect at P.A. Semi, which was acquired by Apple Inc. in 2008. He led Apple’s custom low-power mobile chip efforts with the original A4 processor that powered the iPhone 4*, as well as the subsequent A5 processor.

He will officially start in his new role at Intel on April 30.

https://newsroom.intel.com/news-releases/jim-keller-joins-intel-lead-silicon-engineering/

 

[goldstone77]

Link to Intel Earnings Call
https://www.intc.com/investor-relations/events-and-presentations/events-calendar/default.aspx
Link to Earning presentation
https://www.intc.com/investor-relations/events-and-presentations/events-calendar/event-details/2018/Q1-2018-Intel-Corporation-Earnings-Conference/default.aspx

 

[goldstone77]

Intel hopes to have 10nm hvm by 2nd have of 2019.