Intel's Future Chips: News, Rumours & Reviews

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https://twitter.com/IanCutress/status/989630920276750336

Might be relevant as well... Oh boy... Looks like Intel is pushing what "truth" is to the limit. I wonder if big investors will sue if they find down the road the management did not disclose this information "in full" to them at some point? Maybe they know about it and sneak-selling in bulk? How's the stock market reacting to this earnings call? I haven't seen any comments around this particular tidbit.

Cheers!
 


Intel's stock is up in the after hours. Their numbers are really good, but their are saying misleading statements about 10nm!
 
Question-and-Answer Session 10nm-7nm questions

Ross C. Seymore - Deutsche Bank Securities, Inc.
That's very helpful. For my follow-up question, for either of you, frankly, on the 10-nanometer pushout, do you believe that the competitive lead you have versus your competition is shrinking, or is this a challenge everybody is going to have? And then the gross margins side of that equation, Bob, you said it was going to be a headwind into the full-year guide. Any sort of linearity about when that starts to move from being a headwind to a tailwind would be great. Thanks.
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Brian M. Krzanich - Intel Corp.
Sure, Ross. So let me start with we absolutely have product and process leadership. We're shipping 10-nanometer products today. So I did want to make sure that that was very clear to you, and those are the densest, highest performing products out there.

We're slowing the ramp down as we go and fix these yields, and we're able to do that. A), we understand the yield issues. They're really tied to this being the last technology tied to not having EUV and the amount of multi-patterning and the effects of that on defects. But also, the real strength of 14-nanometer, I mentioned in my prepared remarks that we've done 70% improvements in the performance of that technology over its current lifetime. And we believe it continues to have legs, that we can continue to make improvements, both within that process technology and architecturally. That's really giving us the breathing room to go and make these yield improvements.

So it's really balancing between delivering the world's best products. So we believe our roadmap for 2018 is as strong or stronger than it's ever been. And we have the ability to carry that into 2019, allowing us to get the yields where we want them to be. So the cost and the spending are really in line with what you as a shareholder expect from us.

We believe that if you take a look at others during this timeframe, if you looked at anybody else and said 70% improvement on a technology node, they may rename those nodes as we go through this. And we have always chosen to be really transparent and clean and just say it's improvements on the existing technology rather than renaming. So we believe we have that.

Now as we look out in time, we do see the density. If you just take that component, the density gap is narrowing a bit, but that's out in time. But again, performance is really a function of multiple parts of the process around power and performance and in architecture. And that's why we think our products continue to lead and be the world's standard.
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Stacy Aaron Rasgon - Sanford C. Bernstein & Co. LLC

Hi, guys. Thanks for taking my questions. I wanted to follow up on that 10-nanometer point. So as the volume production pushes out into 2019, given you understand the yield issue supposedly, is this a first half pushout, or does it push out into the second half? And when it actually does ramp, do you think it actually will be the current 10-nanometer process that's shipping, or will that be slipping out to 10-nanometer plus potentially?
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Brian M. Krzanich - Intel Corp.

So I'm just going to correct you. You said that supposedly we have the solutions. We do understand these, and so we do have confidence that we can go and work these issues, Stacy. Right now, like I said, we are shipping. We're going to start that ramp as soon as we think the yields are in line. So I said 2019. We didn't say first or second half, but we'll do it as quickly as we can based on the yield.

The last part of your question about whether will it be a 10 or 10-plus-plus or 10-plus I think was your question, the yield improvements that we're making are just that, more focused on yield. So think of them as improvements to the various edge stuff, the lithography stuff, thin cleans (33:54) and things like that in order to really drive the multi-patterning and, in some cases, multi-multi-patterning, where you have four, five, six layers of patterning to produce a feature. It's really about that. They aren't necessarily around performance.

We do have plans on 10-nanometer already, similar to 14-nanometer, for 10-plus and 10-plus-plus. And so we think all of these technologies now have multiple years of performance improvements built into them as they come off the floor.
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Christopher Brett Danely - Citigroup Global Markets, Inc.

Hey. Thanks, guys. I guess another question on the manufacturing. Can you just talk about why the ramp in 10-nanometer or why the yields have been a little bit slower than expected? Have there been any changes in manufacturing? And then also, should we expect this to extend to future generations as well; i.e., a little bit slower than it had been in the past?
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Brian M. Krzanich - Intel Corp.

Sure, so the issues around 10-nanometer, I'm trying to lay that flat out without getting too deep into the technology. But this is the last technology that doesn't incorporate EUV. And what you also need to understand is that we took very aggressive goals at 10 nanometers. So if you talk about the scaling factor or think about it as the multiple at which you shrink a feature, we took a target of 2.7. So you took any feature and run over 2.7 is the dimensional shrink that you did to this device. For example, on 14-nanometer, we took a target of 2.4, so you're almost 10% more aggressive on 10 nanometers.

And if you look at what is the industry standard, what the foundries and other players are typically doing, they're typically in that 1.5 to 2.0 range. So there, we're maybe 20% more aggressive. So it's very aggressive goals to hit our cost targets and where we want the technology to be. And that combined with the end of life of the immersion scanner before we hit EUV has just created something that's a little bit more difficult.

So that's why I have the confidence that this is not something we're shipping. The transistors work. We know the performance is in line. So it's really just about getting the defects and the costs in line to where we want.

As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in this case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.

And thirdly, we are using some very unique packaging technologies and such that allow us. At 7 nanometers and beyond, we're really moving to a world where you're not going to look at any piece of silicon as being a single node. You're going to use what we're going to call heterogeneous techniques that allow us to use silicon for multiple nodes. So you may use cores from 7 nanometers and IP from 14 nanometers and even as far back as 22 nanometers for the parts that don't need the high performance. And we're able to put those together and make them perform and behave like a single piece of silicon in the package. So really 7 nanometers is quite a bit different, and so I think as a result, we don't expect to see these kinds of impacts on 7 nanometers.
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Timothy Arcuri - UBS Securities LLC

Thank you. I actually had a two-part question on 10-nano. The issues seemed to be going on now for some time, and it's almost as if the design libraries or something are flawed. So I guess the first question is why not skip 10-nanometer and go directly to 7-nanometer? You guys have a lot of EUV experience and it's going to cut out a lot of the multi-pattern layers. So that's the first question.

And number two, the real question is that if you did that, would that be a net drag to gross margin looking out because you never really monetized 10-nanometer? Thanks.
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Brian M. Krzanich - Intel Corp.

Okay, so let me try and answer your question. No, there's nothing wrong with the design libraries or anything like that. The proof of that is that we're shipping product. So if there were basic functionality issues like that, you wouldn't be able to produce and ship the product. Again, as I said, this is all around how many layers are on multi-patterning and the end of life of the immersion for the critical layers.

The second part of your question was would it benefit to just skip to 7 nanometers, and would that have an effect on the capital or the gross margins? The simple answer is no. I don't think that's a good idea. The best answer is there's a lot of learning that will happen that we can carry forward into 7 nanometers just like we carried from 14-nanometer to 10-nanometer.

The other thing is that we still hold – roughly 80% of our capital equipment is fungible to the next node or backwards to the prior node. And so that's why as we've shifted 10-nanometer and 14-nanometer, we were able to do that without shifting our capital expenditures greatly from – we're able to just move the capacity back and forth. The same thing is going to happen between 10-nanometer and 7-nanometer. So you'll have some percentage, and it's always based on demand and how fast things are ramping and all of that. But the equipment will be fungible for the most part between 10-nanometer and 7-nanometer as well.

But no, the right thing to do is exactly what we're doing. This is a unique opportunity we have. There's a lot more performance than 14-nanometer. We can keep driving that. We'll fix the yield issues. If 10-nanometer can have a 10-nanometer, a 10-plus, a 10-plus-plus, you're going to see a lot of products and a lot of performance out of that technology.
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This is Tom's Harware reporting the 10 nm delay.

Intel's 10nm Is Broken, Delayed Until 2019
https://www.tomshardware.com/news/intel-cpu-10nm-earnings-amd,36967.html

The 10nm Problems

Overall, Intel had a stellar quarter, but it originally promised that it would deliver the 10nm process back in 2015. After several delays, the company assured that it would deliver 10nm processors to market in 2017. That was further refined to the second half of this year.
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On the earnings call today, Intel announced that it had delayed high-volume 10nm production to an unspecified time in 2019
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Intel was unwilling to commit to high volume production in the first half of 2019, so it's possible 10nm will be delayed until the second half of the year.
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I guess we should prepare for 14nm++++ and 14nm+++++ refinements
This is nearly 6 years on 14nm from 2014 to 2019
 


Not surprising. New nodes are getting so complex you aren't going to have great yields out of the gate. I wouldn't be surprised if "10nm" [regardless of naming] is around for a while yet.
 
Yeah, Intel's manufacturing process is in the dumpster. When they talked about yields in the earning call they said they have problems, and they know what the problems are, but didn't say when or how they were going to fix those problems. They said they hoped to have their yield problems fixed by 2H of 2019, but gave no assurances. In the call they said 10nm would be the last process they could do without EUV, but other foundries are already implementing it. The big deal comes in play when Intel has been very secretive about it's process while other foundries are publishing their progress openly!
 
We don't know how the yields for GloFo are going right now at all. Also, Intel are most likely implementing EUV on 10nm++.
 


GloFo is just one of many, though. Currently, Intel's biggest adversary in manufacturing is TSMC and Samsung in second place. GloFo comes at a 3rd place, a bit far behind Samsung I'd say.

Cheers!
 
Do we know if Samsung is mass manufacturing anytime soon?

 
Last I check GlobalFoundries was supposed to start 2H 2018-first half 2019. I have to check to see if it has changed.

Edit: Latest article I could find still looking for a time table to mass production.
Globalfoundries: 7 nm to Enable up to 2.7x Smaller Dies, 5 GHz CPUs
by Raevenlord Wednesday, March 7th 2018 13:55
Globalfoundries' Chief Technical Officer, Gary Patton, talked about the future he believes can be possible in future manufacturing processes, calling for particular attention towards the next step in the ladder at 7 nm. Apparently, the 7 nm process at Globalfoundries has received a shot in the arm from the integration of ex IBM engineering specialists (remember that IBM practically paid Globalfoundries to take its manufacturing division of its hands), and the company now expects better than foreseen technical specs and achievements of its 7 nm process.

While a move from 14 nm to 7 nm was expected to provide, at the very best, a halving in the actual size of a chip manufactured in 7 nm compared to 14 nm, Gary Patton is now saying that the are should actually be reduced by up to 2.7 times the original size. To put that into perspective, AMD's 1000 series processors on the Zeppelin die and 14 nm process, which come in at 213 mm² for the full, 8-core design, could be brought down to just 80 mm² instead. AMD could potentially use up that extra die space to either build in some overprovisioning, should the process still be in its infancy and yields need a small boost; or cram it with double the amount of cores and other architectural improvements, and still have chips that are smaller than the original Zen dies.
According to Patton, these die space saving improvements aren't the only thing that has gone on better than they expected on the 7 nm manufacturing process. Patton said that he expects this design to be able to scale pretty well to some 5 GHz operating frequencies. Now, this is the least interesting part of the 7 nm equation, even though it might not seem like it. The ability to scale up to 5 GHz frequencies will of course depend on the architecture's design being able to achieve that operating frequency stably, most of all. And of course, we've already had an historical example of an architecture that aims to go as high as possible in the frequency department with Intel's NetBurst - and we all remember how that went.
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https://www.techpowerup.com/242148/globalfoundries-7-nm-to-enable-up-to-2-7x-smaller-dies-5-ghz-cpus
2nd Edit:
Q15: With the first generation of 7nm, do you expect to be high volume production by the end of the year?

GP: By the end of the year or most likely in early 2019, with a couple of key partners. Our ASIC customers, of which there are quite a few, are also lead users of our 7nm process.
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https://www.anandtech.com/show/12438/the-future-of-silicon-an-exclusive-interview-with-dr-gary-patton-cto-of-globalfoundries
 


They start 7nm production in June, but as far as High volume production, I don't expect it to start until later this year.
Rumor says they will produce Qualcom's Snapdragon 855 as well as next generation Exynos, that are expected to be inside phones by early 2019.

 


Context for this?

Ian already said AMD gave HPET guidelines for Zen v1, but not Zen v1.5 and Intel never gave any. He assumed incorrectly, but that is hardly incompetence. I do agree Ian is arrogant, though, but I don't see why it matter in this particular case.
 
Read above the tweet. Lol

So why have reviewers known about this since last year?
 


That is a different question. In fact, Ian not knowing does not mean what he did was wrong. He measured the huge disparity when Intel activates HPET and now there's evidence of how bad it can affect performance in Intel systems.

I also read it's been asked to Intel in several occasions, but Intel has not given any official answers, AFAIK.

This might well be one of those "ghost hunts" that some people saw as anomalous, but no one gave credit to those sources. It's now being asked again though. I hope Intel gives a straight answer this time.

Cheers!
 
Some first hand info on Intel's 10 nm status. Looks like they are not very optimistic.
High Volume Production is not expected until 2019-Q4.
We all know it's because of low yields. However "low yields" actually means "really very low yields". Single digit yields where suggested. I don't know if such low yields are for the tiny 2-core dies they are producing right now or for bigger dies.
 


That might explain this statement on twitter this morning.


Ashraf Eassa
‏
@TMFChipFool

I remember the days when $INTC was a 4% yielder.

https://twitter.com/TMFChipFool/status/992000785184706560
 


I think Ashraf means financial yield.
Lasts years Intel is yielding "only" a litle over 2% while around 2011 to 2013 yielded above 4%

However the answer to that tweet seems to be refering to 10nm yields 😀

 


Yeah, that's what I was referring too! 😉
 


I actually thought about the economical yield first, but the reply to his tweet got me confused.

Thanks for the clarification.

Cheers!
 
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