No, it's delicate balance of how much IPC they can deliver at a certain clock speed, on a certain process node, at a certain area. Increasing IPC comes at the expense of die area and clock speed. It's not just a dial you can turn up or down, independent of anything else.
It also takes time to increase the sophistication of their designs, which mostly build on what they did in the previous generation. Realistically, they can only change a certain amount between one generation and the next, which goes towards explaining some of the improvements in Zen 3, which was made on mostly the same node as Zen 2 and has only like 10% more die area.
Engineering is a very incremental exercise, which a lot of people might not fully appreciate. You can do all the modeling and estimation you want of a chip, but at some point you just have to build the thing. Then, take detailed measurements, do thorough analysis, and figure out what worked and what didn't, so you can decide what to build on or scrap, in future generations.
Time is also a factor. Not only do they need to do all of the modeling and design, but still leave time for testing, debugging, and a couple respins. And they do a lot of testing, since chip bugs can be so costly. At one point in time, I think the industry average was 2 test engineers for every 1 design engineer.