nm

[velocci]

hi there, when you read about a processor, they give a measurement in nm. for example the new processor from intel is 65nm. what does nm mean?

 

[pat]

nanometer

 

[velocci]

but what exactly is measured in nm? the width of the core?

 

[ir_efrem]

best way i can explain this..umm
well chip die itself is measured in MM (millimeters) would be a MUCH larger number if measured in nm

the process of making a die and all its layers is where the nm measurement comes into play - i do not know what "exactly" is measured in nm(s)

but if you have ever seen a blown up view of a cpu die will will notice a maze of conections and what nots (my technical terms heh)

anyway the smaller the process (90nm vrs 65nm lets say) means all them lines, maze looking what nots and stuff (more technical terms) are physically smaller in size - smaller = less power consumption and more room for extra things

im certain some one out there can attach some real words to my lack of DIE vernacular

hope this helps at least a little

 

[velocci]

so die is the same as core?

 

[Guest]

It is a measure of the smallest feature size possible per a given technology. The circuits are formed by photoimaging the various layers as the process requires. The technology limitations in a given photoimaging process results in its maximum resolution which defines a minimum feature size possible for that particular process.

 

[velocci]

huh?

 

[Guest]

Like in your camera, the number of megapixels determine how closely you can zoom in on the picture before you start to see granularization. The same problem exists in chip manufacture. Since they are using a photoimaging process the granularity of the source image results in a finite feature size limit.

In Intels new process 65 billionths of a meter is the finest detail that any feature of the circuit may reliably have.

edit oops had my decimal in the wrong spot

 

[velocci]

ok i get it now, but can you explain in more detail about the photoimaging process? or point to a site that describes it? thanks

Like in your camera, the number of megapixels determine how closely you can zoom in on the picture before you start to see granularization. The same problem exists in chip manufacture. Since they are using a photoimaging process the granularity of the source image results in a finite feature size limit.

In Intels new process 65 billionths of a meter is the finest detail that any feature of the circuit may reliably have.

edit oops had my decimal in the wrong spot

 

[Admiral_Cecil]

Hello

Nanometer:

One billionth of a meter. Nanometers are used to measure the wavelengths of light. See angstrom and metric system.

CPU's went from 130 to 90 to 65 (notice how much smaller)

Besides you see those large capcitors and chips on your mobo, imagine those so small you need an electron microscope to see it.

 

[DesertGator]

It is a measure of the smallest feature size possible per a given technology. The circuits are formed by photoimaging the various layers as the process requires. The technology limitations in a given photoimaging process results in its maximum resolution which defines a minimum feature size possible for that particular process.

That is not quite accurate. The nm mesurement is the linewidth in the die. During the photoimaging process (actually, it's just easier to have this link explain it since I'm somewhat of a lousy teacher).

The nm width of the line is directly related to the wavelength of the circuit. Have you noticed that most of the companies have kind of hit the wall with regards to chip speeds? This has to do partly with the wavelengths of these frequencies (actually the quarter-wavelength) and some of the more annoying reflective properties of higher frequency RF circuitry.

In any case, the less width (read: less room) the lines use, the more transistors that can put on the die and therefore the more processing power that can be generated..

 

[sonoran63]

I believe the nm refers to the wavelength of the light used. Note that 65nm is already out of the visible spectrum and into ultraviolet.

Here's a nice little litho glossary: ftp://download.intel.com/technology/silicon/EUV_Glossary_080204.pdf

And some cool 65nm presentations with electron microscope images of die features can be found here: http://www.intel.com/technology/silicon/65nm_technology.htm

 

[Guest]

The nm mesurement is the linewidth in the die.

Ya sure I'll buy that. I'm sure my understanding of the actual process isn't ideal. BTW interesting but very dry read. I hate all that legal type technical writing.

Have you noticed that most of the companies have kind of hit the wall with regards to chip speeds?

Signaling is getting quite fast these days. A nanometer or so is a significant distance compared to a wavelength, ie as you mention transmission line, cross talk, and radiation start being problems. It strikes me as somewhat bass ackwards (not that it isn't logical) that chip designers are finally hitting the same shortcomings in their design models which has plagued system/board designers since electronics was invented. It used to be that [/quote]digital guys thought only of things like boolean logic and Karnot maps, but now everyone will need a little analog designer in them to succeed.

The "new" problems can all be dealt with using the much less user friendly Maxwell equation design rules rather than the fairly user friendly Kirchoff/Ohms law design rules. This particular hurdle can be cleared, not that there aren't many different and difficult to deal with hurdles waiting just beyond it.

 

[ir_efrem]

the photo imaging process is kinda nifty actually - if you can find a place that explains it well witout boring you to tears with to much technical jargon

(VERY) basically they do this - take the design they want to make the for the chip - make it BIG - take a picture of this - shrink that image - using the negative of the image though - not the actual image itself - this is pretty much where our current technology limits come into play - changing image sizes makes for a loss in clairty, nanometers are pretty small

then through some kinda process - prolly some type of bonding process that involves something like umm chroming an object or anodizing, powder coating, etc etc (which is adding a negative or positive charge to said item and letting the chemicals bond using the oposite charge) - after all, this negative image has to let actual electricity flow through it before it becomes a microchip

what happens after this i dunno - somehow the package is bonded to the silicon and the metal pins applied (needless to say very precise crap happening here) super controled invironments, no dust, temp changes, etc etc etc

ive prolly taken a very technical process and reduced it to something very bastardized - but im fairly certain that this is *basically* how the process happens