Darkbreeze :
How is C6/C7 implemented any differently on 4th-8th gen than on 3rd gen, or 1st gen for that matter?
The difference isn't in the implementation or meaning per se, but in how fast the CPU can go in/out of sleep: prior to Haswell, going in/out of C6 sleep used to be a very slow operation (milliseconds scale) but with Haswell, this can happen thousands of times per second (microsecond scale) and to achieve power savings from going in/out of deep-sleep ~100X faster, the VRM and the PSU by extension, need to be able to cope with those much faster, bigger and more frequent transients.
Prior to Haswell, there wasn't an explicit power specification on how quickly the PSU had to react to load changes. Starting with Haswell which introduced those much faster C6 transitions, Intel's power spec now requires that PSUs be able to cope with load transients of 8A/10us IIRC. That's sleep to full power or full power to sleep in 10us for a 96W CPU. If the PSU can't keep up with that while C6 is enabled, the CPU crashes, which is why many people have to disable C6 sleep to make their Haswell and newer PCs stable when using lower quality and/or older PSUs.