Intel's Future Chips: News, Rumours & Reviews

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goldstone77

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I believe the reasoning behind the dual ring bus, to decrease power consumption with more cores.
 

jimmysmitty

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Plausible considering that even on the same 14nm their HEDT platform doesn't seem to use nearly as much power.
 

goldstone77

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10nm Cannon Lake NUC at Major US Retailers
by Anton Shilov on December 3, 2018 10:45 AM EST

Amazon, Newegg, and Walmart have started to sell Intel’s Crimson Canyon NUC that is based on Cannon Lake processors produced using the company’s 10 nm process technology. Availability of the NUC8i3CY-series UCFF PCs at major retailers indicated that Intel is making its 10 nm CPUs in rather sizeable volumes.
https://www.anandtech.com/show/13669/10nm-cannon-lake-nuc-at-major-retailers?utm_source=twitter&utm_medium=social

This appears to be the same dual cores that were release in China last year, in limited quantities, for laptops with AMD GPUs. Ian Cutress has had a laptop and somewhat promised a review since last year, but has keep coming up with excuses for not reviewing. Now, with wider availability maybe we will get some reviews now.

Intel Core i3-8121U
2C/4T
2.2 - 3.2 GHz
4 MB cache
15 W TDP
Graphics AMD Radeon 540 GPU
 

audiospecaccts

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I got a j5005-itx computer in (canyon-lake) that was brought to me for debugging slowdowns. Shame on you Microsoft! You haven't fixed the virtualization and storport issues you had ever since Longhorn. To make matters worse, you left debugging on the storport module! Leaving the developer's logging on really makes a safe os does it?!? your not even sending the data back encrypted. So you left me no alternative but to reveal the way to disable it:

[HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\StorPort]
"TelemetryPerformanceEnabled"=dword:00000000
"TelemetryErrorDataEnabled"=dword:00000000
"TelemetryDeviceHealthEnabled"=dword:00000000
"LogControlEnable"=hex(b):00,00,00,00,00,00,00,00

Also no MBR and CMS on board?!? So are they using a software translation for the mbr subsystem that is still there? If so, it will make the system slow as the hard drive fills.
 

goldstone77

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Intel's 10nm HP 80.61MTr/mm² UHP 67.18 MTr/mm²
TSMC's(AMD) 7nm HPC 66 MTr/mm² MTr/mm²



https://fuse.wikichip.org/news/2004/iedm-2018-intels-10nm-standard-cell-library-and-power-delivery/
 

jimmysmitty

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This parts important:

We’re looking to confirm this price with other vendors, if it's with/without tax or what a boutique builder might charge to add it into the system. We know that some online retailers have starting listing parts at just over $4000, so it's an interesting disparity between the two. But we thought you should know what we’ve been told. Thoughts below!
The price has not been confirmed with retail channels just a boutique OEM and we all know boutique OEMs mark prices up a lot. Hell even Dell does. Their SSD pricing is normally 20-30% above retail SSDs.

And I am not surprised with the socket change. Its basically the 28 core server part but designed for single sockets. There was never a point where anyone should have expected this to be a LGA2066 part.
 
I know no one can predict the future, but this question is aimed towards people who might know more than i do and can provide me the answers based on my gaps of knowledge on Intel's existing architecture:

Do you think Intel has reached the limit with ring bus architecture? Is the 9900k the most cores they'll be able to fit on that die and will they have to move over to mesh for core counts higher than that? Will they be able to expand ring bus architecture to allow for more cores and quad channel memory? The only reason I ask is because this architecture is superior in gaming performance and if they have to move to mesh for higher core counts, this kind of defeats the purpose.
 
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jimmysmitty

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I know no one can predict the future, but this question is aimed towards people who might know more than i do and can provide me the answers based on my gaps of knowledge on Intel's existing architecture:

Do you think Intel has reached the limit with ring bus architecture? Is the 9900k the most cores they'll be able to fit on that die and will they have to move over to mesh for core counts higher than that? Will they be able to expand ring bus architecture to allow for more cores and quad channel memory? The only reason I ask is because this architecture is superior in gaming performance and if they have to move to mesh for higher core counts, this kind of defeats the purpose.
Of course they can do more cores and memory channels on a ring bus. They already did. The i7 6950X was a 10 core and their HEDT platform has been 3 and 4 channels of RAM since its inception all using the ring bus.

That said, while its is superior now it might not be in the future as Intel finds ways to better optimize it and applications start to take advantage of the Mesh bus design.
 
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DavidC1

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That said, while its is superior now it might not be in the future as Intel finds ways to better optimize it and applications start to take advantage of the Mesh bus design.
There's nothing advantageous about the Mesh in low core designs. Mesh is a compromise. It allows scaling number of cores, and when you have lots of cores it allows LLC cache latency to be more consistent.

Mesh is meant for server chips where it has 28 cores. In there, the latency is same as the ring bus design because it needs 3 or so rings to cover them all, and you need things like repeaters. But in the case of lower core count chips, the advantage is in favor of the ring bus, because it clocks higher and is lower latency.
 
There's nothing advantageous about the Mesh in low core designs. Mesh is a compromise. It allows scaling number of cores, and when you have lots of cores it allows LLC cache latency to be more consistent.

Mesh is meant for server chips where it has 28 cores. In there, the latency is same as the ring bus design because it needs 3 or so rings to cover them all, and you need things like repeaters. But in the case of lower core count chips, the advantage is in favor of the ring bus, because it clocks higher and is lower latency.
Very interesting, thank you! So if you're using applications that optimize for higher core counts, it would make more sense to choose mesh. How many cores can you have on ring bus before there is a negative effect?
 

jimmysmitty

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There's nothing advantageous about the Mesh in low core designs. Mesh is a compromise. It allows scaling number of cores, and when you have lots of cores it allows LLC cache latency to be more consistent.

Mesh is meant for server chips where it has 28 cores. In there, the latency is same as the ring bus design because it needs 3 or so rings to cover them all, and you need things like repeaters. But in the case of lower core count chips, the advantage is in favor of the ring bus, because it clocks higher and is lower latency.
Considering AMDs assault in the core count department it seems Intels decision to move to a Mesh Bus over a Ring bus on their HEDT makes sense. As Intel will no doubt need ot move to more cores per chip to match AMDs overall performance, especially if the third iteration of Ryzen does what rumors seem to state it will which is close not only the IPC gap but also the clock speed gap.

I am sure Intel made the decision for a reason.
 

jimmysmitty

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Until these get used I don't see any threat. I assume Intel is being targeted since they are the majority of desktop and HPC/Server CPUs so we will always see more flaws or exploits.

What gets me is that Universities are the ones doing this and they always publish the data. If it was an unknown flaw/exploit it is now a known flaw/exploit for someone to use.
 

Darkbreeze

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I sort of agree, but I also believe that just because the masses didn't know about it, doesn't mean that a handful of nefarious hackers, government agencies (Foreign and domestic) or troll farm infiltrators didn't know about it and weren't using it in ways that weren't even being looked for because nobody knew to be looking for it.
 

jimmysmitty

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I sort of agree, but I also believe that just because the masses didn't know about it, doesn't mean that a handful of nefarious hackers, government agencies (Foreign and domestic) or troll farm infiltrators didn't know about it and weren't using it in ways that weren't even being looked for because nobody knew to be looking for it.
Agrred although I think not releasing it to the masses is better and rather working with Intel/AMD/whoever is a better way to go about it. Then possibly announce the issue and its fix at the same time to keep it from becoming a useable exploit.

Of course with all these exploits its actual use will depend as well. Spectre and Meltdown was generally a HPC environment exploit rather than consumer.
 

jimmysmitty

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Well, they did say there is no possible fix via software, so in this case maybe they figured what's the point of waiting if it can't be mitigated anyhow?
Because software isn't firmware which might be able to fix it. And Intel did release a statement stating this would rely on the software to not follow the proper procedures and for DRAM to not have mitigation in it that it probably should have. Of course Intel will say what they need to cover their butts however I would not be surprised if software devs do take shortcuts and if DRAM manufactures as well do take shortcuts to save on costs.
 
Just going to point out something ironic: The Itanium architecture is immune to all variants of Spectre/Meltdown, due to being an in-order architecture that doesn't include all those wonderful x86 speedhacks that are now being taken advantage of.

Seriously, if Intel designed a new CPU architecture that was both secure and massively parallel today, it would essentially look like the Itanium architecture.
 

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