jimmysmitty
Champion
Cazalan :
gamerk316 :
Yeah, the root problem is we really can't shrink Silicon based chips anymore. Intel thinks they can do 7nm, if they build in redundancy (which means the chips will be VERY space ineffective, expensive to produce, and not very profitable). Point is, unless a replacement is found within the next few years, we're two die shrinks (about 5-6 years) from hitting a brick wall, and we go from 10% yearly CPU performance improvements, to 0% yearly CPU performance improvements.
Its those brick walls that force innovation. I don't recall that many issues at 7nm. IBM was saying the real hurdles will arrive below the 5nm level.
Anyway the 3D packaging and 450mm wafers will add significantly to the improvements. The surface has only been scratched there. Hardware is known to fail for some time. Higher end systems have repair capabilities in place already for RAM, drive, and CPU cores. Economies of scale will drive those features into everyday consumer products.
The tools are constantly improving to better plan for those failures as well.
https://www.semiwiki.com/forum/content/5085-finfet-reliability-analysis-device-self-heating.html
450mm wafers wont help on process size but will increase cores per wafer and increase profits.
3D will help to add cores/cache etc but again not the process.
Intel never said they can't do Silicon at 7nm just that they do not plan to due to the issues they have already run into on 14nm and 10nm with Silicon (parasitic capacitance for example) due to Silicon being stretched to its limits. IBM has a 7nm process but had to move to Silicon-Germanium to do it.
Within the next few years Silicon will probably start being used less in consumer processors.